FIG. 8 is a perspective view showing a structure of a conventional microwave monolithic IC (MMIC). In FIG. 8, reference numeral 100 designates an MMIC chip and reference numeral 1 designates a gallium arsenide substrate on which first and second active elements 101 and 102 formed of field effect transistors (FET), a capacitor element 103, an inductor element 104, a resistor element 105 or the like are disposed. In addition, reference numerals 131 to 135 designate bonding pads arranged at the periphery of the semiconductor substrate 1 and reference numerals 111 to 113 designate signal transmission lines which connect the elements to each other or to a predetermined bonding pad. In addition, reference numerals 121 and 122 designate first and second air bridge wirings which connect the bonding pads over the first and second active elements 101 and 102, respectively, and reference numeral 106 designates a via hole which connects the predetermined bonding pad to an electrode 130 on a back surface.
In order to obtain a good operational characteristic at a high frequency such as a microwave band, a low resistance metal layer is formed on the conductor layers such as the electrodes of FET, the boding pads and the inductor element. An applicant of the present invention has already disclosed a method for forming a low resistance upper part gate electrode on a base gate electrode in Japanese Patent Publication 62-274673 as an example of a technique capable of being applied to such a microwave band device.
FIG. 9(d) is a sectional view taken along a line IXd --IXd in FIG. 8, which shows in detail the bonding pad 133 connected to the FET element. In FIG. 9(d), reference numeral 2 designates an FET electrode on the semiconductor substrate 1, reference numeral 3 designates a passivation film for protecting the surface of the substrate, reference numeral 9 designates an electrolytic Au layer on the FET electrode 2 with an intervening metal adhesion layer 5 and a feeder Au layer 6. As the metal adhesion layer 5, a Ti layer or a Cr layer is used and the feeder Au layer 6 serves as a cathode electrode for applying a current at the time of electrolytic plating. In addition, reference numeral 9a designates a rough morphology portion of the electrolytic Au layer 9.
Next, the manufacturing method will be described. Each element of the MMIC is formed on the semiconductor substrate and then the base metal layer and its upper electrolytic Au layer of the bonding pads and the signal transmission lines are sequentially formed.
The method for forming the electrolytic Au layer on the bonding pad is described in detail hereinafter. After the FET electrode is formed, the passivation film 3 is deposited on the whole surface of the semiconductor substrate 1 and then selectively removed by reactive ion etching or plasma etching to expose the surface of the FET electrode 2. Then, a first resist layer 4 is applied thereto and patterned to form an opening 4a at the FET electrode 2. Then, the Ti adhesion layer 5 and the feeder Au layer 6 are sequentially formed by sputtering (FIG. 9(a)).
Then, a second resist layer 8 is applied thereto and patterned to form an opening 8a where the FET electrode 2 is arranged (FIG. 9(b)). Then, the substrate is immersed in a plating solution and a current is applied with the feeder Au layer 6 as a cathode to form the electrolytic Au layer 9 in the opening 8a of the second resist layer 8 (FIG. 9(c)). Then, the second resist layer 8, the feeder Au layer 6, the adhesion layer 5 and the first resist layer 4 are sequentially removed and then the bonding pad having a sectioned structure shown in FIG. 9(d) is obtained.
However, according to the above method, the surface of the electrolytic Au layer which is in contact with the base metal layer is rough and the nonuniformity causes its appearance to be damaged or prevents the pad from being detected at the time of automated bonding. In FIG. 8, dotted marks show that the surface is rough.
More specifically, in thermal processing, for example for forming the passivation film 3, as the base metal layer 2 such as the FET electrode formed by vapor deposition is crystallized, the size of the crystal grains increases as shown in FIG. 10(a) and (b). In other words, the surface of the base metal layer 2 becomes rough. Therefore, even when the Ti adhesion layer or the feeder Au layer 6 is formed between the electrolytic Au layer 9 and the base metal layer 2, the electrolytic Au layer 9 is rough because of the surface of the base metal layer 2 in which the crystal grain size is increased (FIG. 10(c)). The grain size changes unevenly because of crystal growth with a preferred orientation of the plating relative to the &lt;111&gt; surface of the electrolytic Au layer 9 or the surface condition of the base metal layer 2. Thus, the electrolytic Au 9 shows morphology 9a in which large crystalline grains roughly exist.
As a result, the luster is changed between or in the pattern, for example between different signal transmission lines or in one signal transmission line, the luster nonuniformity damages not only plated appearance but also automation using auto-bonding in packaging process.
In the above electrode forming method, when the Ti adhesion layer 5 and the feeder Au layer 6 are removed by wet etching, the electrolytic Au layer 9 is etched away at the same time, causing the surface of the layer 9 to become irregular. However, as a method for solving this problem, the applicant of the present invention has already disclosed a method for etching the lower Ti adhesion layer and the feeder Au layer while the surface of the electrolytic Au layer 9 is covered with the Ti layer in Japanese Patent Publication No. 63-318145.